The present disclosure herein relates to a method of fabricating a semiconductor package, and more particularly, to a method of fabricating a semiconductor package having enhanced process reliability.
As a stacked package that has been typically implemented by using a wire bonding technology needs high performance, the development of a 3D package that employs the through silicon via (TSV) technology is being performed. The 3D package is obtained by the vertical stacking of devices having various functions and may implement the expansion of memory capacity, low-power, a high transmission rate, and high efficiency.